The present invention relates to analog-to-digital (AD) converters and more particularly to techniques for fabrication of multi-step AD converters and analog switches which are formed on MIS type or MOS type semiconductor integrated circuit devices, especially, the technique used for converting a high-speed analog signal such as a video signal into a digital signal in, for example, digital televisions, video cassette recorders and video tape recorders.
Two-step CMOS AD converters are disclosed in JP-A-63-157522, "A CMOS 40 MHz 8 b 105 mW Two-Step ADC" by N. Fukushima et al, ISSCC 89/WEDNESDAY, FEB. 15, 1989/WEST GRAND BALLROOM, pp. 14-15, "An 8-b 50-MHz 225-mW SUBMICRON CMOS ADC USING SATURATION ELIMINATED COMPARATORS" by T. Matsuura et al. IEEE 1990 CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp. 6.4.1.-6.4.4.
A presupposition required for correct conversion to be performed in the two-step or sub-flash ADC is that an analog signal to be converted into upper bit data is the same as an analog signal to be converted into a lower bit data. In other words, an analog signal to be sampled and held for comparison by means of upper sample-and-hold circuits must be the same as an analog signal to be sampling and held for comparison by means of lower sample-and-hold circuits.
Practically, however, the timing for an analog signal to be sampled by the upper sample-and-hold circuits cannot perfectly coincide with the timing for the analog signal to be sampled by the lower sample-and-hold circuits because of a difference in edge shift between sampling clocks due to unevenness in transfer characteristics and circuit constants. Therefore, there is a very slight difference between the timings for sampling by the upper sample-and-hold circuits and lower sample-and-hold circuits and even within this time difference, the analog signal such as a video signal whose level changes at a very high rate will change greatly in its level. Consequently, the level of the analog signal sampled and held for comparison by the upper sample-and-hold circuits and lower sample-and-hold circuits is different for the two types of sample-and-hold circuits and hence continuity between the upper bit data and lower bit data cannot be ensured, resulting in conversion errors.